Method and apparatus for latency specific duty cycle correction
US6768697B2 · kind B2 · utility
15Cited by
5References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The illustrated embodiments relate to a control circuit that uses a latency signal to generate an output signal. The latency is used to create a control signal that is dependent on the latency signal. The control signal is used to select from among multiple input sources. The selected input source is used to create an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.