Array of transistors with low voltage collector protection
US6770935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Jun 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/307
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.