Semiconductor device with SI-GE layer-containing low resistance, tunable contact
US6770954B2 · kind B2 · utility
16Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Nov 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.