Semiconductor package and substrate thereof
US6770979B2 · kind B2 · utility
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1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2003 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Mar 24, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor package characterized by having at least one cavity defined in a substrate and at least one buffer pad disposed in the at least one cavity. The semiconductor package includes a semiconductor chip disposed on the substrate, at least one conductive trace connecting with the buffer pad and at least one bonding wire electrically connecting the semiconductor chip to the buffer pad. The buffer pad has a thickness larger than the thickness of the conductive trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.