System and method for testing integrated circuit modules
US6771087B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Jun 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Verification testing of modules packaged within an integrated circuit are conducted utilizing I/O ports of the integrated circuit for inputting or outputting incoming and outgoing signals, with three sets of externally controlled, tri-state buffers provided for each module. A first set selectively connects predetermined I/O contacts of each module interconnected to contacts of other modules, a second set selectively connects predetermined I/O contacts of each module to the I/O ports and a common test bus, and a third set applies the last logic state on each I/O contact before isolation by a buffer from the first set. Whenever a module is selected for testing, the current value that appears on each I/O contact that is connected to other modules is stored in its corresponding bus holder, so as to essentially prevent DC leakage currents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.