System and method for reducing a leakage current associated with an integrated circuit
US6771118B2 · kind B2 · utility
3Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/56
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method for reducing a leakage current in an integrated circuit is provided that includes controlling one or more inputs of an integrated circuit such that one or more logic elements within the integrated circuit are set to one or more selected values. The selected values produce a minimum leakage current associated with the integrated circuit when the integrated circuit is operating in a standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.