Method and apparatus for providing row redundancy in nonvolatile semiconductor memory
US6771541B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2003 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Feb 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a NOR-type flash memory of either the ETOX or virtual ground type that is programmed using electron injection and erased using FN tunneling, and that has row redundancy, the typical sequence of operations used for an embedded sector erase, namely the Preprogram, Preprogram Verify, Erase, Erase Verify, Post-Program Verify, and Post-Program operations, need not be performed for the data cells on bad or shorted rows or in unused redundant rows. Instead, the bad or shorted rows or the unused redundant rows are suitably biased so that the threshold voltages of the data cells in these rows tend to converge to a threshold voltage near the UV erased threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.