Multi-master computer system with overlapped read and write operations and scalable address pipelining
US6772254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Jun 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus. Programming apparatus alters the read and write pipeline logic for address pipelining
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.