System and method for reducing power consumption in a data processor having a clustered architecture
US6772355B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Sep 15, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters, an instruction cache and a power-down controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The power-down controller monitors the instruction cache and each instruction execution pipeline to identify power-down conditions associated with the same and, in response to an identified power-down condition, at least one of: (i) bypasses performance of at least a portion of subsequent ones of the N processing stages associated with an executing instruction, (ii) powers down the instruction cache, and (iii) powers down the data processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.