Anthony Jarvis
21Patents
4h-index
19Co-inventors
60Inventor score
Filing activity: Dec 29, 2000 → Mar 30, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8181005B2 | Hybrid branch prediction device with sparse and dense prediction caches | Physics | 36 | Active |
| US6772355B2 | System and method for reducing power consumption in a data processor having a clustered architecture | Emerging Cross-Sectional Technologies | 11 | Expired |
| US8578141B2 | Loop predictor and method for instruction fetching using a loop predictor | Physics | 7 | Active |
| US10635591B1 | Systems and methods for selectively filtering, buffering, and processing cache coherency probes | Physics | 6 | Active |
| US6922773B2 | System and method for encoding constant operands in a wide issue processor | Physics | 3 | Expired |
| US6807628B2 | System and method for supporting precise exceptions in a data processor having a clustered architecture | Physics | 3 | Expired |
| US6865665B2 | Processor pipeline cache miss apparatus and method for operation | Physics | 2 | Expired |
| US7757066B2 | System and method for executing variable latency load operations in a date processor | Physics | 2 | Active |
| US7093107B2 | Bypass circuitry for use in a pipelined processor | Physics | 2 | Expired |
| US11256505B2 | Using loop exit prediction to accelerate or suppress loop mode of a processor | Emerging Cross-Sectional Technologies | 1 | Active |
| US8667257B2 | Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit | Physics | 1 | Active |
| US8788797B2 | Combined level 1 and level 2 branch predictor | Physics | 1 | Active |
| US10915322B2 | Using loop exit prediction to accelerate or suppress loop mode of a processor | Emerging Cross-Sectional Technologies | 1 | Active |
| US7028164B2 | Instruction fetch apparatus for wide issue processors and method of operation | Physics | 1 | Expired |
| US12153927B2 | Merged branch target buffer entries | Physics | 0 | Active |
| US12282776B2 | Hybrid parallelized tagged geometric (TAGE) branch prediction | Physics | 0 | Active |
| US7143268B2 | Circuit and method for instruction compression and dispersal in wide-issue processors | Physics | 0 | Expired |
| US9778934B2 | Power efficient pattern history table fetch in branch predictor | Physics | 0 | Active |
| US11416253B2 | Multiple-table branch target buffer | Physics | 0 | Active |
| US11216279B2 | Loop exit predictor | Physics | 0 | Active |
| US10713054B2 | Multiple-table branch target buffer | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.