Patent · US Expired

Insertable block tile for interconnecting to a device embedded in an integrated circuit

US6772405B1 · kind B1 · utility

6Cited by

85References

19Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Andy H. Gan · San Jose, US
Nigel G. Herron · San Jose, US

Key dates

Filing date	Jun 13, 2002
Grant date	Aug 3, 2004
Priority date	—
Expiry date	Aug 4, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method and apparatus for an insertable block tile is described. More particularly, a reserved area in an integrated circuit layout is removed, and terminated conductive line information is extracted from a layout database affected by the removal. The terminated conductive line information is used to create extensions or pins of the conductive lines terminated, as well as to identify signals associated with those terminated conductive lines. These physical or layout names and coordinates are mapped and then translated to logic names and coordinates for placement and routing to create the insertable block tile.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.