Formation of a shallow trench isolation structure in integrated circuits
US6773975B1 · kind B1 · utility
4Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Dec 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.