Inventor · Santa Clara, CA, US

Sundar Narayanan

35Patents
7h-index
23Co-inventors
69Inventor score

Filing activity: Jan 2, 2001 → Mar 31, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6943126B1 Deuterium incorporated nitride Electricity 17 Expired
US9595670B1 Resistive random access memory (RRAM) cell and method for forming the RRAM cell Electricity 17 Active
US6774012B1 Furnace system and method for selectively oxidizing a sidewall surface of a gate conductor by oxidizing a silicon sidewall in lieu of a refractory metal sidewall Electricity 14 Expired
US9697874B1 Monolithic memory comprising 1T1R code memory and 1TnR storage class memory Electricity 14 Active
US9741765B1 Monolithically integrated resistive memory using integrated-circuit foundry compatible processes Electricity 12 Active
US7189652B1 Selective oxidation of gate stack Electricity 12 Expired
US7351663B1 Removing whisker defects Electricity 7 Expired
US6803321B1 Nitride spacer formation Electricity 6 Expired
US10319908B2 Integrative resistive memory in backend metal layers Electricity 6 Active
US9209396B2 Regulating interface layer growth with N2O for two-terminal memory Electricity 6 Active
US6794269B1 Method for and structure formed from fabricating a relatively deep isolation structure Electricity 6 Expired
US9425046B1 Method for surface roughness reduction after silicon germanium thin film deposition Electricity 5 Active
US9437814B1 Mitigating damage from a chemical mechanical planarization process Electricity 5 Active
US7371637B2 Oxide-nitride stack gate dielectric Electricity 5 Expired
US6773975B1 Formation of a shallow trench isolation structure in integrated circuits Electricity 4 Expired
US10062845B1 Flatness of memory cell surfaces Electricity 4 Active
US8445381B2 Oxide-nitride stack gate dielectric Electricity 4 Active
US10693062B2 Regulating interface layer formation for two-terminal memory Electricity 3 Active
US6905893B1 Method and structure for determining a concentration profile of an impurity within a semiconductor layer Electricity 2 Expired
US6803330B2 Method for growing ultra thin nitrided oxide Electricity 2 Expired
US10522754B2 Liner layer for dielectric block layer Electricity 2 Active
US10290801B2 Scalable silicon based resistive memory device Electricity 2 Active
US6964929B1 Method of forming a narrow gate, and product produced thereby Electricity 2 Expired
US7172914B1 Method of making uniform oxide layer Electricity 1 Expired
US10115819B2 Recessed high voltage metal oxide semiconductor transistor for RRAM cell Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.