Transferable device-containing layer for silicon-on-insulator applications
US6774010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Jan 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer descri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.