Method of forming dual-damascene structure
US6774031B2 · kind B2 · utility
5Cited by
9References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Dec 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.