Method integrating polymeric interlayer dielectric in integrated circuits
US6774037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Aug 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.