Semiconductor device using fuse/anti-fuse system
US6774439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2001 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Mar 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.