Method and apparatus for characterizing a delay locked loop
US6774687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.