Test method and apparatus for source synchronous signals
US6775637B2 · kind B2 · utility
7Cited by
18References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 2003 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | May 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and associated apparatus for testing devices outputting source synchronous signals using automated test equipment (“ATE”). An output data signal and an output clock signal from such a source synchronous device under test are delayed using a delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.