Performance adder for tracking occurrence of events within a circuit
US6775640B1 · kind B1 · utility
6Cited by
9References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A performance adder for providing a running total of performance values within an integrated circuit chip. The performance adder is triggered by various performance events as determined through multiplexer logic for detecting occurrence of a particular performance event. The multiplexer logic can also trigger the performance adder through atomic, edge, toggle, or on/off signals related to the performance events or through a logical function of a combination of performance events. The performance adders can be used to compute average latency of a component in the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.