Layout design process and system for providing bypass capacitance and compliant density in an integrated circuit

US6775812B2 · kind B2 · utility

Assignee

• HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. · US

Inventors

• John Andrew Francis Cloudman · Fort Collins, US
• Jonathan Lachman · Fort Collins, US
• Nicholas Michell · Fort Collins, US

Key dates

• Filing date: Jul 17, 2002
• Grant date: Aug 10, 2004
• Expiry date: Sep 2, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/00

Abstract

An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density measurement associated with the IC's fabrication flow.