Inspection system and semiconductor device manufacturing method
US6775817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2001 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Oct 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system are provided for analyzing defects having the potential to become electrical failures, during the inspection of particles and/or pattern defects of a wafer used in the manufacture of electronic devices such as semiconductor integrated circuits. Defect map data is processed along with failure probability data. Next, defect-dependent failure probability calculations are made to obtain the failure probability of each defect in the defect map data. That data is then used to prepare failure-probability-added defect map data. Further, a selection process of defects to be reviewed is used to reorder and filter defects from the failure-probability-added defect map data, thus selecting one or more defects for review.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.