Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6777265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.