Method and system to manufacture stacked chip devices
US6777648B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Jan 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system for electrically interconnecting a semiconductor device and a component is presented. The semiconductor device includes a dielectric portion on at least one face thereof. Similarly, the component includes a dielectric portion on at least one face thereof. The device and component are constructed and arranged to be stacked and bonded together. A first laser selectively ablates the respective dielectric portions of the device and component. The ablating creates a starting pad on the device or component and a destination pad on the device or component. A second laser deposits a conductor along a path between the starting pad and destination pad. As such, smaller, more condensed electronic packages may be fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.