Semiconductor die package including drain clip
US6777800B2 · kind B2 · utility
135Cited by
18References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Oct 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die package including a semiconductor die including a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip having a major surface is electrically coupled to the drain region. A gate lead is electrically coupled to the gate region. A source lead is electrically coupled to the source region. A non-conductive molding material encapsulates the semiconductor die. The major surface of the drain clip is exposed through the non-conductive molding material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.