Patent · US Expired

FIFO memory architecture

US6777979B1 · kind B1 · utility

17Cited by

2References

20Claims

0Family size

Assignee

Lattice Semiconductor Corporation · US

Inventors

Jinghui Zhu · San Jose, US
Jin Ni · Taiping, CN
Ju Shen · San Jose, US
Tong-Sheng Wang · Milpitas, US

Key dates

Filing date	Dec 31, 2002
Grant date	Aug 17, 2004
Priority date	—
Expiry date	Feb 13, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17744
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A FIFO coordinates with registers of a programmable semiconductor device, wherein the registers are clocked according to an internal clock and words are written into the FIFO according to a write clock. The FIFO includes a read counter responsive to the internal clock to identify a current read address in the FIFO. At a given cycle of the internal clock, the word stored at the current read address of the FIFO may be registered within the registers of the programmable semiconductor device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.