Memory device array having a pair of magnetic bits sharing a common conductor line
US6778421B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2002 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Mar 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetic random access memory (MRAM) device having parallel memory planes is disclosed. Each memory plane includes a first magneto-resistive cross point plane of memory cells, a second magneto-resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a first plurality of bit lines, each of the first plurality of bit lines coupling one or more cells from the first plane to at least one other memory cell in the first plane, a second plurality of bit lines, each of the second plurality of bit lines coupling one or more cells from the second plane to at least one other memory cell in the second plane, and a plurality of unidirectional elements. Further, the one unidirectional element couples a first memory cell from the first plane to a selected word line and a selected bit line in a first conductive direction and a second unidirectional element couples a second cell from the second plane to the selected word line and selected bit line in a second conductive direction. The device further provides for a unidirectional conductive path to form from a memory cell in the first plane to a memory cell in the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.