Processing semiconductor devices having some defective input-output pins
US6778933B2 · kind B2 · utility
0Cited by
9References
17Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques to process semiconductor devices whose input-output (I/O) pins are only partially operative is able to accommodate substantially all possible combinations of operative I/O pin patterns. Semiconductor devices are tested to determine which I/O pins are operative. A code representing which I/O pins are operative is then associated with each tested device. The generated codes are used to selectively combine two or more semiconductor devices to form a component capable of providing the function of a single fully operational semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.