Method and apparatus for executing a long latency instruction to delay the restarting of an instruction fetch unit
US6779122B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Aug 25, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A micro-code sequence to reduce the rate of change of current required by a processor coming out of a sleep mode when the processor clock is resumed. After stopping the instruction fetch unit, an instruction with a long latency, or execution time, can be initiated by the micro-code before the processor clock is stopped to enter a sleep mode. When the sleep mode is exited by resuming the processor clock, the instruction with the long execution time is completed before restarting the instruction fetch unit. This prevents a portion of the processor circuitry from resuming operation immediately when the clock is resumed, which also delays some of the current demands made by that portion of the circuitry. This creates a more gradual increase in the current required by the processor when exiting a sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.