Conductively doped strontium titanate barrier intermediate a silicon underlayer and an epitaxial metal oxide film
US6781176B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory cell formed on a monocrystalline silicon underlayer, either an epitaxial silicon contact plug to a transistor source or drain or silicon gate region for which the memory cell forms a non-volatile gate. A conductive barrier layer of vanadium or niobium substituted strontium titanate is epitaxially grown over the silicon, and a lower metal oxide electrode layer, a ferroelectric layer and an upper metal oxide electrode layer are epitaxially grown on the barrier layer. No platinum barrier is needed beneath the ferroelectric stack. The invention can be applied to many other functional oxide devices including micromachined electromechanical (MEM) devices and ferromagnetic tri-layer devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.