Memory sorting method and apparatus
US6781363B2 · kind B2 · utility
7Cited by
5References
37Claims
0Family size
Inventor
Key dates
| Filing date | Jun 21, 2001 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Nov 28, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/135
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus performs testing, sorting, and packaging of partially defective semiconductor memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.