Circuit for testing an integrated circuit
US6781398B2 · kind B2 · utility
7Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit for testing an integrated circuit, includes a test signal input for receiving a test signal from the integrated circuit and a reference signal input for receiving a reference signal. A comparator is in communication with the test signal input and with the reference signal input. The comparator is configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error. The error signal, if present, is stored in an error memory, in communication with the comparator output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.