Early power-down digital memory device and method
US6781911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Jul 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and devices for a memory system are disclosed. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, “early”. The device shuts down some circuitry, such as address and command registers, immediately upon receipt of the early power-down command. Other device components, e.g., those involved in servicing the burst read or write, remain active at least until their portion of the command has been completed. In some embodiments, the early power-down command can be issued concurrently with an active-mode command as an option to that command, freeing a memory controller from having to schedule and issue power-down commands separately. Significant power savings, as compared to those obtained with prior-art memory device power-down modes, are possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.