Linked list DMA descriptor architecture
US6782465B1 · kind B1 · utility
47Cited by
12References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1999 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Oct 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A linked list DMA descriptor includes an indication of a number of data pointers contained in a subsequent DMA descriptor. The number of data pointers contained in the subsequent DMA descriptor is preferably contained in the memory address of the subsequent DMA descriptor. The number of data pointers is stored by the DMA controller and controls how many read cycles are performed when processing the subsequent DMA descriptor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.