Statistical decision system
US6782500B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2000 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31932
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.