Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
US6783862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Nov 8, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/31663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.