Methods for forming aligned fuses disposed in an integrated circuit
US6784043B2 · kind B2 · utility
4Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Feb 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and a second fuse is disposed in the second conductive layer in alignment with the first fuse and provides a second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.