Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
US6784101B1 · kind B1 · utility
Inventors
Key dates
| Filing date | May 16, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Sep 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.