Inventor · Cupertino, CA, US

Bin Yu

643Patents
61h-index
333Co-inventors
93Inventor score

Filing activity: Jun 7, 1995 → Jun 7, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6646307B1 MOSFET having a double gate Electricity 1,438 Expired
US6475869B1 Method of forming a double gate transistor having an epitaxial silicon/germanium channel region Electricity 577 Expired
US6682973B1 Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications Electricity 547 Expired
US6706571B1 Method for forming multiple structures in a semiconductor device Electricity 543 Expired
US6429484B1 Multiple active layer structure and a method of making such a structure Electricity 309 Expired
US6921963B2 Narrow fin FinFET Electricity 253 Expired
US6312995A "MOS transistor with assisted-gates and ultra-shallow ""Psuedo"" source and drain extensions for ultra-large-scale integration" Electricity 244 Expired
US6391753B1 Process for forming gate conductors Electricity 203 Expired
US6645797B1 Method for forming fins in a FinFET device using sacrificial carbon layer Electricity 199 Expired
US6835618B1 Epitaxially grown fin for FinFET Electricity 190 Expired
US6562665B1 Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology Electricity 185 Expired
US6066533A MOS transistor with dual metal gate structure Electricity 178 Expired
US6709982B1 Double spacer FinFET formation Electricity 174 Expired
US6693333B1 Semiconductor-on-insulator circuit with multiple work functions Electricity 167 Expired
US6475890B1 Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology Electricity 161 Expired
US6611029B1 Double gate semiconductor device having separate gates Electricity 158 Expired
US6764884B1 Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device Electricity 158 Expired
US6458662B1 Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed Electricity 155 Expired
US6551885B1 Low temperature process for a thin film transistor Electricity 152 Expired
US6784101B1 Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation Electricity 150 Expired
US6787424B1 Fully depleted SOI transistor with elevated source and drain Electricity 141 Expired
US6245618A Mosfet with localized amorphous region with retrograde implantation Electricity 139 Expired
US6380019B1 Method of manufacturing a transistor with local insulator structure Electricity 138 Expired
US6552377B1 Mos transistor with dual metal gate structure Electricity 138 Expired
US6534373B1 MOS transistor with reduced floating body effect Electricity 134 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.