Method for planarizing a copper interconnect structure
US6784107B1 · kind B1 · utility
3Cited by
7References
21Claims
0Family size
Inventors
Key dates
| Filing date | Mar 18, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Mar 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of planarizing a copper interconnect structure using an atomic layer removal (ALR) technique to planarize a copper layer. In one embodiment, the ALR process performs a plurality of cycles, each cycle having a period of forming a film of copper fluoride on the copper layer and a period of removing the film of copper fluoride. The ALR process is repeated until a barrier layer beneath the copper layer is then etched to expose a dielectric material. The remaining copper forms a conductive line that is substantially coplanar with the dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.