Chun YAN
20Patents
3h-index
16Co-inventors
56Inventor score
Filing activity: Mar 18, 2003 → Nov 12, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6841484B2 | Method of fabricating a magneto-resistive random access memory (MRAM) device | Electricity | 25 | Expired |
| US10205002B2 | Method of epitaxial growth shape control for CMOS applications | Electricity | 3 | Active |
| US6784107B1 | Method for planarizing a copper interconnect structure | Electricity | 3 | Expired |
| US10002759B2 | Method of forming structures with V shaped bottom on silicon substrate | Electricity | 2 | Active |
| US10043667B2 | Integrated method for wafer outgassing reduction | Electricity | 2 | Active |
| US9905412B2 | Method and solution for cleaning InGaAs (or III-V) substrates | Electricity | 2 | Active |
| US10115607B2 | Method and apparatus for wafer outgassing control | Electricity | 2 | Active |
| US9653291B2 | Method for removing native oxide and residue from a III-V group containing surface | Electricity | 1 | Active |
| US10243063B2 | Method of uniform channel formation | Electricity | 1 | Active |
| US10236190B2 | Method for wafer outgassing control | Emerging Cross-Sectional Technologies | 1 | Active |
| US10504717B2 | Integrated system and method for source/drain engineering | Electricity | 0 | Active |
| US11256057B2 | Lens module with electromagnetic prothction and electronic device using the same | Physics | 0 | Active |
| US10438796B2 | Method for removing native oxide and residue from a III-V group containing surface | Electricity | 0 | Active |
| US9472416B2 | Methods of surface interface engineering | Electricity | 0 | Active |
| US9805914B2 | Methods for removing contamination from surfaces in substrate processing systems | Electricity | 0 | Active |
| US10147596B2 | Methods and solutions for cleaning INGAAS (or III-V) substrates | Electricity | 0 | Active |
| US9852903B2 | System and method in indium-gallium-arsenide channel height control for sub 7nm FinFET | Electricity | 0 | Active |
| US10332739B2 | UV radiation system and method for arsenic outgassing control in sub 7nm CMOS fabrication | Electricity | 0 | Active |
| US9653282B2 | Silicon-containing substrate cleaning procedure | Electricity | 0 | Active |
| US9865706B2 | Integrated process and structure to form III-V channel for sub-7nm CMOS devices | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.