Process for forming metalized contacts to periphery transistors
US6784501B2 · kind B2 · utility
10Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Mar 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process and apparatus directed to forming metal plugs in a peripheral logic circuitry area of a semiconductor device to contact both N+ and P+ doped regions of transistors in the peripheral logic circuitry area. The metal plugs are formed after all high temperature processing used in wafer fabrication is completed. The metal plugs are formed without metal diffusing into the active areas of the substrate. The metal plugs may form an oval slot as seen from a top down view of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.