Content addressable memory with power reduction technique
US6785152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Aug 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result. A second CAM may include entries corresponding to the entries in the first CAM, and each entry may be coupled to receive the indication of the compare result from the corresponding entry of the first CAM and is configured to generate a second compare result which includes the first compare result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.