Mark Pearce
13Patents
4h-index
13Co-inventors
57Inventor score
Filing activity: May 15, 2001 → Mar 24, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6816932B2 | Bus precharge during a phase of a clock signal to eliminate idle clock cycle | Physics | 22 | Expired |
| US10585825B2 | Procedures for implementing source based routing within an interconnect fabric on a system on chip | Electricity | 7 | Active |
| US6877085B2 | Mechanism for processing speclative LL and SC instructions in a pipelined processor | Physics | 6 | Expired |
| US6646899B2 | Content addressable memory with power reduction technique | Physics | 6 | Expired |
| US6785152B2 | Content addressable memory with power reduction technique | Physics | 4 | Expired |
| US10853282B2 | Arbitrating portions of transactions over virtual channels associated with an interconnect | Electricity | 3 | Active |
| US11003604B2 | Procedures for improving efficiency of an interconnect fabric on a system on chip | Electricity | 3 | Active |
| US10838891B2 | Arbitrating portions of transactions over virtual channels associated with an interconnect | Electricity | 3 | Active |
| US7162613B2 | Mechanism for processing speculative LL and SC instructions in a pipelined processor | Physics | 2 | Expired |
| US11340671B2 | Protocol level control for system on a chip (SOC) agent reset and power management | Emerging Cross-Sectional Technologies | 2 | Active |
| US11640362B2 | Procedures for improving efficiency of an interconnect fabric on a system on chip | Electricity | 1 | Active |
| US7076582B2 | Bus precharge during a phase of a clock signal to eliminate idle clock cycle | Physics | 1 | Expired |
| US11914440B2 | Protocol level control for system on a chip (SoC) agent reset and power management | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.