Semiconductor memory device capable of performing high-frequency wafer test operation
US6785173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Jan 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.