Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology
US6785703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2001 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is on at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry_ signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry_ signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.