DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism
US6785776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Aug 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The data processing system further comprises operational protocol providing a pair of instructions/commands that are utilized to complete a DMA Write operation. The pair of instructions is DMA_Write_No_Data and DMA_Write With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire “DMA ownership” of a cache line that is to be written. The initial ownership of the cache line is marked by a weak DMA state (D1), which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive (D2) state, then the next cache line in a weak DMA state transitions to a DMA Exclusive (D2) state, which forces a retry of snooped operations until the DMA_Write_With_Data transact…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.