Method and apparatus for software prefetching using non-faulting loads
US6785796B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2000 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for altering code to effectively hide main memory latency using software prefetching with non-faulting loads prefetches data from main memory into local cache memory at some point prior to the time when the data is requested by the CPU during code execution. The CPU then retrieves its requested data from local cache instead of directly seeing the memory latency. The non-faulting loads allow for safety and more flexibility in executing the prefetch operation earlier because they alleviate the concern of incurring a segmentation fault, particularly when dealing with linked data structures. Accordingly, the memory access latency that the CPU sees is essentially the cache memory access latency. Since this latency is much less than the memory latency resulting from a cache miss, the overall system performance is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.