Methods and apparatus for facilitating physical synthesis of an integrated circuit design
US6785875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Jan 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.