Semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof and a method of fabricating the semiconductor package
US6787393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Feb 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.